A semiconductor imaging chip is an integrated circuit containing a two dimensional array of photosensitive diodes and amplifiers known as “active pixel sensors” (APS). A “pixel” is a single picture element, such as one dot of a given color. The imaging chip is placed in the focal plane of a digital camera and exposed to an image during the camera shutter time interval. Diodes in the silicon substrate detect the light, and generate electrons, which accumulate negative charge on n-type junctions in the semiconductor circuit substrate.
Initially, the photodiodes are reset to a positive voltage. If a mechanical or electromechanical shutter is used, the shutter is opened and a focused image is projected onto the surface of the chip. Incident light discharges the initial positive voltage on each photodiode by an amount proportional to the total light flux during the time that the camera shutter is open (called the image exposure time or shutter time interval). In an electronic camera using a semiconductor imaging chip, the mechanical shutter may be eliminated. A mechanical shutter is simulated by resetting a given photodiode, and then reading out the voltage on the photodiode a short time later. The time between reset and readout is the image exposure time for that particular photodiode.
The photodiode array is arranged in rows and columns. The resulting voltage on each of the photodiodes is read out by means of scanning and signal processing circuits, which are typically included on the imaging chip. Individual APS cells are addressed by accessing each row of the APS cell array individually and sensing the respective outputs of the corresponding APS cells in the selected row from the plurality of columns in the array.
APS Cell
Each APS cell contains a photodiode and a small amplifier formed by field effect transistors (FET) operated as a source follower (a current amplifier) circuit. A suitable active pixel sensor containing a photodiode and four transistors forming a source follower amplifier circuit is disclosed in U.S. Pat. No. 4,445,117 to Gaalema et al. The disclosed APS cell includes a first control line to access the photodiode during readout, and a second separate control line to reset the photodiode after readout in preparation for the next image exposure. The advantage of the APS cell shown by Gaalema et al., is that it uses metal oxide semiconductor field effect transistors (MOSFET), instead of the charged coupled devices (CCD) of the prior art.
Improved APS Cell Array
An improvement to the layout of the APS cell of Gaalena et al. is disclosed in U.S. Pat. No. 5,083,016 to Wyles et al. The circuit layout efficiency of the array of Gaalena APS cells is improved by Wyles by merging the access and control lines into single access/control lines. That is, the access line of the current row of APS cells is merged with the reset line of the previous row of APS cells into single access/reset line that performs both functions. Thus in Wyles et al., each access/reset control line simultaneously accesses the current row of APS cells and resets the previous row of APS cells, thereby improving layout efficiency, especially for large arrays of very small pixels.
However, by merging access and reset control lines the operational flexibility of having separate control lines to independently reset and access the current APS cell on separate lines is lost. For example, merged access and reset control lines impede the ability to control the image exposure time. Normally, rows of pixels are held in reset until ready to begin sensing light. However, holding a row of pixels in a reset condition is not possible when using merged access and reset control lines, because holding a merged access/reset control line in a reset condition for one APS cell would interfere with reading (accessing) the adjacent APS cells in the next row. With respect to pattern noise, the perceived disadvantage due to the merged access and control lines is that it is no longer possible to observe the reset value of the current pixel. Merged access and reset control lines impedes the ability to cancel pattern noise and control image exposure time.
Source of Pattern Noise in CMOS Semiconductor Imaging Chips
Pattern noise results from the small differences between individual FET transistors in each APS cell. In particular, each source follower buffer in each APS cell will have a (different) offset voltage between the photodiode voltage and the output column bus voltage, which offset voltage is equal to about one gate-to-source threshold of the FET source follower transistor. Since there are random variations of the offset voltage between individual FET transistors on the order of some tens of millivolts, the random offset voltages produce a fixed pattern of noise arising from the imaging chip itself, which pattern noise will be superimposed on the imaged illumination. The pattern noise caused by the variation in APS offset voltage is unacceptably large for most applications, and particularly in the case of low power cmos semiconductor fabrication.
As indicated, in a conventional APS cell, there are separate bus lines for access and reset control functions. Conventionally, these separate lines are used to cancel the pattern noise caused by the random source follower offset voltages of each APS cell. The pattern noise is cancelled by reading out the APS pixel signal value and sampling it (using the access control line), then resetting the APS (using the reset control line), and sampling the APS reset signal value immediately after the reset (using the access control line). In such manner, the signal value from the APS cell is sampled before, during and after the current APS cell is reset.
The difference between the sampled (stored) APS pixel signal value and the measured offset voltage in the reset condition (the stored APS reset signal value) is proportional to the true pixel (photodiode) illumination. By taking the difference between the previously stored sampled APS pixel signal value and the current APS reset signal value, an output pixel signal value is produced in which the source follower buffer offsets are cancelled. In other words, by subtracting the reset signal value of the current APS cell from the pixel signal value of the current APS cell, the pattern noise due to the source follower offset is cancelled. However, to use the above process to eliminate pattern noise, separate access and reset control lines to the current APS cell are needed.